This invention relates generally to apparatus that is operable in a low power standby or "sleep" mode in the event of a power failure and specifically to television receivers incorporating such a feature.
Most modern television receivers incorporate a microprocessor for performing one or more ancillary functions as well as conventional tuning. For example, homing channels may be programmed into the receiver such that each time the receiver is turned on, it will tune either to a specific channel or to the channel it was previously tuned to. Also, clock and channel number displays are controlled and operated by the microprocessor. In many hotel/motel receivers, AM/FM clock radios are incorporated and controlled by the microprocessor. The microprocessor includes a memory that needs to be refreshed periodically. Normally, this is accomplished by internal apparatus that operates from the power line and is not a problem as long as the receiver is not disconnected from the line or the power line voltage does not drop significantly. In particular, a microprocessor identified as Matsushita No. MN 15251G10, incorporates two clock signals, one of approximately 4 MHz and another of 32 KHz. The 4 MHz clock is the normal timing clock and is operable when the receiver is operating normally, that is, it is receiving normal input voltage. The 32 KHz clock is activated by an appropriate signal applied to a low voltage sense pin on the microprocessor to force the microprocessor into a so-called sleep mode. In the sleep mode, only minimal power demands are made by the microprocessor to keep certain memory and clock timing circuits alive for as long as possible during a power failure.
There are many circuits used in consumer electronic devices for maintaining essential timing and memory functions during a power outage. For example, many clock radios incorporate a nickel cadmium battery for maintaining the timekeeping function of the clock during a power outage, even though the display may be extinguished. An extended power outage will, of course, ultimately result in failure of this feature once the battery is discharged. The battery is automatically kept charged from the power line during normal operation of the apparatus.
The present invention uses an already present electrolytic capacitor at the power input of the microprocessor as the source of energy for continuing sleep mode operation of the microprocessor during a power failure. This capacitor is coupled across the output of the 5 volt regulator that supplies regulated voltage to the microprocessor. The present invention forces the microprocessor into its sleep mode in the event of a low or zero voltage condition while the capacitor is fully charged and still capable of supporting the essential timekeeping and memory functions of the microprocessor.